`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date: 11/17/2021 09:29:27 PM
// Design Name: 
// Module Name: main_workmode_module
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 工作状态控制模块，控制工作在计时状态还是设置状态。需要设置两种工作状态下的输入和输出。输出需要设置多路选择和两种工作状态的使能端。
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module workmode(
    input clk,
    input rst_n,
    input key_change,
    input [3:0] out0,
    input [3:0] out1,
    input [3:0] out2,
    input [3:0] out3,
    input [3:0] work0,
    input [3:0] work1,
    input [3:0] rest0,
    input [3:0] rest1,
    output reg [3:0] fin0,
    output reg [3:0] fin1,
    output reg [3:0] fin2,
    output reg [3:0] fin3,
    output reg en_fun,
    output reg en_config
    );
    reg working_mode;
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n)
            working_mode <= 0;
        else if (key_change)
            working_mode <= ~working_mode;
    end
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
                fin0 <= 0;
                fin1 <= 0;
                fin2 <= 0;
                fin3 <= 0;
                en_fun <= 0;
                en_config <= 0;
        end
        else
        case (working_mode)
            0:begin
                fin0 <= out0;
                fin1 <= out1;
                fin2 <= out2;
                fin3 <= out3;
                en_fun <= 1;
                en_config <= 0;
            end
            1:begin
                fin0 <= work0;
                fin1 <= work1;
                fin2 <= rest0;
                fin3 <= rest1;
                en_fun <= 0;
                en_config <= 1;
            end 
        endcase
    end
endmodule
